IME Forms Chip-On-Wafer Consortium

Chip-on-wafer technology could pave the way for higher-performance, slimmer and more cost-effective electronic devices.

AsianScientist (Dec. 29, 2014) – A*STAR’s Institute of Microelectronics (IME) has formed a Chip-on-Wafer (CoW) Consortium to enable semiconductor firms to develop commercially-viable capabilities for making 3D chipsets.

Conventional Chip-on-Wafer bonding techniques used for making 3D chipsets rely on a solder-assisted thermo-compression bonding process that takes more than 15 seconds and at a minimum of 300 degrees Celsius to complete. This method, which attaches the chip to a piece of semiconductor wafer, slows the overall production process and results in higher manufacturing costs.

There are also capability limitations in existing solder-assisted bonding technologies to support shrinking microelectronic systems. Melted solder bonding tends to spread and bridge with neighboring solders, and this prevents the scaling down of the pitch, or distance between wirings in an integrated circuit.

The consortium is working on overcoming such challenges by using low temperature copper-copper (Cu-Cu) diffusion bonding. This technique involves the diffusion of copper atoms to form metallic bonding and eliminates the long solder-assisted bonding process. This reduces overall manufacturing time and costs, and enables higher levels of 3D chipset integration.

The members of the new consortium are ON Semiconductor, KLA-Tencor, Panasonic Factory Solutions Asia Pacific (Panasonic), Singapore Epson Industrial Pte Ltd (Plating Division), Tera Probe, Inc, and Tokyo Electron Ltd.

IME and its partners have successfully demonstrated Chip-on-Wafer bonding with Cu-Cu diffusion bonding technology at a lower temperature of 200 degrees Celsius. This reduced the pitch from the average of 40 µm to 10 µm and also lowered production costs. This allows chip device manufacturers to better integrate 3D chipsets such as complementary metal-oxide semiconductor (CMOS) image sensors, signal processors and memory stacks. The consortium aims to reduce the pitch further to 6 µm to open up new possibilities in microelectronics.

Professor Kwong Dim-Lee, Executive Director of IME, said, “We are excited to be taking the lead in this research collaboration with leading industry players by equipping them with a ready Chip-on-Wafer packaging technology. We will continue to work towards pushing the frontiers of 3D chip integration and drive market competitiveness in the value chain.”

“We strongly believe that CoW bonding technology with Cu-Cu bonding will be the breakthrough technology for future 3D IC integration. We also expect that CoW bonding technology will contribute to improve productivity and cost reduction, in addition to technology development,” said Mr. Yuichiro Watanabe, CEO of Tera Probe. Inc.


Source: A*STAR; Photo: Jack Spades/Flickr/CC.
Disclaimer: This article does not necessarily reflect the views of AsianScientist or its staff.

Asian Scientist Magazine is an award-winning science and technology magazine that highlights R&D news stories from Asia to a global audience. The magazine is published by Singapore-headquartered Wildtype Media Group.

Related Stories from Asian Scientist